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low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 8737i-11 revision c 7/16/15 1 ?2015 integrated device technology, inc. g eneral d escription the 8737i-11 is a low skew, high performance differential-to-3.3v lvpecl clockgenerator/divider. the 8737i-11 has two selectable clock inputs. the clk, nclk pair can acceptmost standard differential input levels. the pclk, npclk pair can accept lvpecl, cml, or sstl input levels.the clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew characteristics make the 8737i-11 ideal for clock distribution applications demanding well de ned performance and repeatability. f eatures ? two divide by 1 differential 3.3v lvpecl outputs; two divide by 2 differential 3.3v lvpecl outputs ? selectable differential clk, nclk or lvpecl clock inputs ? clk, nclk pair can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? pclk, npclk supports the following input types: lvpecl, cml, sstl ? maximum output frequency: 650mhz ? translates any single ended input signal (lvcmos, lvttl, gtl) to lvpecl levels with resistor bias on nclk input ? output skew: 75ps (maximum) ? part-to-part skew: 300ps (maximum) ? bank skew: bank a - 30ps (maximum) bank b - 45ps (maximum) ? 3.3v operating supply ? -40? to 85? ambient operating temperature ? available in lead-free rohs-compliant package b lock d iagram p in a ssignment 8737i-11 20-lead tssop 6.50mm x 4.40mm x 0.92 package body g package top view
low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 2 revision c 7/16/15 t able 2. p in c haracteristics t able 1. p in d escriptions number name type description 1v ee power negative supply pin. 2 clk_en power pullup synchronizing clock enable. when high, clock outputs follow clock input. when low, q outputs are forced low, nq outputs are forced high. lvcmos / lvttl interface levels. 3 clk_sel input pulldown clock select input. when high, selects pclk, npclk inputs. when low, selects clk, nclk inputs. lvcmos / lvttl interface levels. 4 clk input pulldown non-inverting differential clock input. 5 nclk input pullup inverting differential clock input. 6 pclk input pulldown non-inverting differential lvpecl clock input. 7 npclk input pullup inverting differential lvpecl clock input. 8 nc unused no connect. 9 mr input pulldown active high master reset. when logic high, the internal dividers are reset. when low, the master reset is disabled. lvcmos / lvttl interface levels. 10, 13, 18 v cc power positive supply pins. 11, 12 nqb1, qb1 output differential output pair. lvpecl interface levels. 14, 15 nqb0, qb0 output differential output pair. lvpecl interface levels. 16, 17 nqa1, qa1 output differential output pair. lvpecl interface levels. 19, 20 nqa0, qa0 output differential output pair. lvpecl interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k
revision c 7/16/15 8737i-11 data sheet 3 low skew 1/2 differential-to- 3.3v lvpecl clock generator t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able inputs outputs mr clk_en clk_sel selected source qa0, qa1 nqa0, nqa1 qb0, qb1 nqb0, nqb1 1 x x x low high low high 0 0 0 clk, nclk disabled; low disabled; high disabled; low disabled; high 0 0 1 pclk, npclk disabled; low disabled; high disabled; low disabled; high 0 1 0 clk, nclk enabled enabled enabled enabled 0 1 1 pclk, npclk enabled enabled enabled enabled after clk_en switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in figure 1. in the active mode, the state of the outputs are a function of the clk, nclk and pclk, npclk inputs as described in table 3b. inputs outputs input to output mode polarity clk or pclk nclk or npclk qax nqax qbx nqbx 0 0 low high low high differential to differential non inverting 1 1 high low high low differential to differential non inverting 0 biased; note 1 low high low high single ended to differential non inverting 1 biased; note 1 high low high low single ended to differential non inverting biased; note 1 0 high low high low single ended to differential inverting biased; note 1 1 low high low high single ended to differential inverting note 1: please refer to the application information section, ?iring the differential input to accept single ended levels? f igure 1 - clk_en t iming d iagram
low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 4 revision c 7/16/15 t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v?%, t a = -40? to 85? t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v?%, t a = -40? to 85? t able 4c. d ifferential dc c haracteristics , v cc = 3.3v?%, t a = -40? to 85? symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 3.135 3.3 3.465 v i ee power supply current 55 ma symbol parameter test conditions minimum typical maximum units i ih input high current nclk v in = v cc = 3.465v 5 a clk v in = v cc = 3.465v 150 ? i il input low current nclk v in = 0v, v cc = 3.465v -150 ? clk v in = 0v, v cc = 3.465v -5 ? v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc - 0.85 v note 1: for single ended applications, the maximum input voltage for clk, nclk is v cc + 0.3v. note 2: common mode voltage is de ned as v ih . symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current clk_en v in = v cc = 3.465v 5 a clk_sel, mr v in = v cc = 3.465v 150 ? i il input low current clk_en v in = 0v, v cc = 3.465v -150 ? clk_sel, mr v in = 0v, v cc = 3.465v -5 ? a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 73.2?/w (0 lfpm) storage temperature, t stg -65? to 150? note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
revision c 7/16/15 8737i-11 data sheet 5 low skew 1/2 differential-to- 3.3v lvpecl clock generator t able 5. ac c haracteristics , v cc = 3.3v?%, t a = -40? to 85? t able 4d. lvpecl dc c haracteristics , v cc = 3.3v?%, t a = -40? to 85? symbol parameter test conditions minimum typical maximum units f max output frequency 650 mhz t pd propagation delay; note 1 clk, nclk ? 650mhz 1.2 1.8 ns pclk, npclk ? 650mhz 1.1 1.7 ns tsk(o) output skew; note 2, 4 75 ps tsk(b) bank skew; note 4 bank a 30 ps bank b 45 ps tsk(pp) part-to-part skew; note 3, 4 300 ps t r output rise time 20% to 80% @ 50mhz 300 700 ps t f output fall time 20% to 80% @ 50mhz 300 700 ps odc output duty cycle 47 50 53 % all parameters measured at 500mhz unless noted otherwise. the cycle-to-cycle jitter on the input will equal the jitter on the output. the part does not add jitter. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: de ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 4: this parameter is de ned in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units i ih input high current v in = v cc = 3.465v 150 ? v in = v cc = 3.465v 5 a i il input low current v in = 0v, v cc = 3.465v -5 ? v in = 0v, v cc = 3.465v -150 ? v pp peak-to-peak input voltage 0.3 1 v v cmr common mode input voltage; note 1, 2 v ee + 1.5 v cc v v oh output high voltage; note 3 v cc - 1.4 v cc - 0.9 v v ol output low voltage; note 3 v cc - 2.0 v cc - 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v note 1: common mode voltage is de ned as v ih . note 2: for single ended applications, the maximum input voltage for pclk, npclk is v cc + 0.3v. note 3: outputs terminated with 50 to v cc - 2v.
low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 6 revision c 7/16/15 p arameter m easurement i nformation o utput s kew d ifferential i nput l evel 3.3v o utput l oad ac t est c ircuit p art - to -p art s kew o utput r ise /f all t ime p ropagation d elay o utput d uty c ycle /p ulse w idth /p eriod
revision c 7/16/15 8737i-11 data sheet 7 low skew 1/2 differential-to- 3.3v lvpecl clock generator a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609.
low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 8 revision c 7/16/15 the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination i nputs : clk/nclk i nput : for applications not requiring the use of the differential input, both clk and nclk can be left oating. though not required, but for additional protection, a 1k resistor can be tied from clk to ground. pclk/npclk i nput : for applications not requiring the use of a differential input, both the pclk and npclk pins can be left oating. though not required, but for additional protection, a 1k resistor can be tied from pclk to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left oating. we recommend that there is no trace attached. both sides of the differential output pair should either be left oating or terminated.
revision c 7/16/15 8737i-11 data sheet 9 low skew 1/2 differential-to- 3.3v lvpecl clock generator p ower c onsiderations this section provides information on power dissipation and junction temperature for the 8737i-11. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8737i-11 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i cc_max = 3.465v * 55ma = 190.6mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 4 * 30mw = 120mw total power _max (3.465v, with all outputs switching) = 190.6mw + 120mw = 310.6mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125?. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used . assuming a moderate air ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6?/w per table 6 below. therefore, tj for an ambient temperature of 85? with all outputs switching is: 85? + 0.311w * 66.6?/w = 105.7?. this is well below the limit of 125? this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5?/w 98.0?/w 88.0?/w multi-layer pcb, jedec standard test boards 73.2?/w 66.6?/w 63.5?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 20- pin tssop, f orced c onvection
low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 10 revision c 7/16/15 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ?(v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ?(v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 4. lvpecl d river c ircuit and t ermination
revision c 7/16/15 8737i-11 data sheet 11 low skew 1/2 differential-to- 3.3v lvpecl clock generator r eliability i nformation t ransistor c ount the transistor count for 8737i-11 is: 510 t able 7. ja vs . a ir f low t able for 20 l ead tssop ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 114.5?/w 98.0?/w 88.0?/w multi-layer pcb, jedec standard test boards 73.2?/w 66.6?/w 63.5?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 12 revision c 7/16/15 p ackage o utline - g s uffix for 20 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 symbol millimeters minimum maximum n20 a -- 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa -- 0.10
revision c 7/16/15 8737i-11 data sheet 13 low skew 1/2 differential-to- 3.3v lvpecl clock generator t able 9. o rdering i nformation part/order number marking package shipping packaging temperature 8737agi-11lf ics8737ai11l 20 lead ?ead-free tssop tube -40? to 85? 8737AGI-11LFT ics8737ai11l 20 lead ?ead-free tssop tape & reel -40? to 85? note: parts that are ordered with an?f suf x to the part number are the pb-free con guration and are rohs compliant.
low skew 1/2 differential-to- 3.3v lvpecl clock generator 8737i-11 data sheet 14 revision c 7/16/15 revision history sheet rev table page description of change date a 8 added termination for lvpecl outputs section. 6/3/02 a 12 6 7 pin description table - revised mr description. 3.3v output load test circuit diagram, revised vee equation from ?1.3v ?0.135v to ?-1.3v ?0.165v? revised output rise/fall time diagram. 8/19/02 b t2 t9 1 2 8 13 features section added lead-free bullet. pin characteristicst table - changed c in from 4pf max. to 4pf typical. added recommendations for unused input and output pins. ordering information table - added lead-free part/order number, marking and note. updated format throughout the datasheet. 1/12/06 c t4d 5 9 - 10 lvpecl dc characteristics table -corrected v oh max. from v cc - 1.0v to v cc - 0.9v; and v swing max. from 0.9v to 1.0v. power considerations - corrected power dissipation to re ect v oh max in table 4d. 4/13/07 c t9 13 15 updated datasheets header/footer with idt from ics. removed ics pre x from part/order number column. added contact page. 8/4/10 c t9 13 ordering information - removed leaded devices. updated data sheet format. 7/16/15
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